1. Field of the Invention
The present invention relates to a semiconductor wafer in which normal semiconductor memory portions and redundant memory portions for replacing malfunctioning normal memory cells are arranged in the form of a matrix on a semiconductor substrate. More specifically, the invention relates to a semiconductor memory device in which the semiconductor memory portion is equipped with a required number of redundant memory portions, and to a method of separating the semiconductor memory devices from the semiconductor wafer.
2. Description of the Related Art
In a semiconductor memory device such as dynamic random access memory (DRAM), in general, a redundant memory cell array and a fuse circuit for controlling redundancy are provided close to a normal memory cell array. In a device such as a DRAM or the like, when a memory cell malfunctions in the normal memory cell array, a line to which the memory cell is connected (i.e., a row line along the direction of word lines or a column line along the direction of bit lines) is replaced by a corresponding line in the redundant memory cell array by using a fuse circuit, in order to replace the normal memory cell that is malfunctioning.
In recent years, however, it has been attempted to further decrease the size of the semiconductor memory device (chip). As the size decreases, however, the ratio of areas occupied by the redundant memory cell array and the fuse circuit increases relative to the chip, serving as a principal factor which makes it difficult to decrease the chip size and to increase the degree of integration.
To cope with this, there has heretofore been employed a technology as disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 6-325589 according to which a fuse to be cut by a laser beam is arranged on a scribe line of a wafer, and another fuse to be melt-cut is arranged in a chip together with the redundant memory cell array. According to this technology, the fuse is cut by a laser beam to produce fuse information and a predetermined voltage is applied through a pad formed on the scribe line to trim the fuse for melt-cutting. In other words, the fuse to be cut by a laser beam is arranged outside the chip to decrease the area of the chip. However, this technology, too, imposes limitation on decreasing the size of the chip due to the presence of a redundant memory cell array in the chip.
Another technology has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. 5-54695 according to which the redundant memory cells are so arranged that they will be shared by two memory cell array regions. In this technology, either one of the memory cell array regions is selected by using a switching element, and a defective memory cell in the selected memory cell array region is substituted with a redundant memory cell, in order to enhance the rate of relieving defective memory cells. However, this technology does not allow decreasing the chip size. That is, this technology cannot solve the problem of decreasing the chip size since the redundant memory cells are provided in the semiconductor memory device (chip).
As a further technology, Japanese Examined Patent Publication (Kokoku) No. 7-28012 discloses a semiconductor memory wherein redundant memory cell groups are arranged along the four sides of the normal memory cell group, in order to make uniform the shape of the memory cells in the normal memory cell group. According to this technology, the normal memory cell group is uniform in shape in order to decrease the chip size. Even with this technology, however, a limitation is imposed on decreasing the chip size, since the redundant memory cell groups are provided in the semiconductor memory (i.e., in the chip).
As a still further technology, Japanese Unexamined Patent Publication (Kokai) No. 6-5098 discloses a semiconductor memory device having a non-volatile redundant memory cell portion formed on a chip for recording inspection data during the inspection of the wafer. According to this technology, after the assembling is completed, the detailed electric characteristics are inspected and sorted based upon the inspection data in the redundant memory cell portion, so that the inspection and sorting can be easily accomplished without the need of writing data. However, the redundant memory cell portion used in this technology is not used to relieve the normal memory cell that is malfunctioning but is used to record the inspection data. Besides, this technology gives no consideration to decreasing the chip size.